![]() ![]() In 56G applications, hardware developers often seek complete clock tree solutions guaranteeing sub-100 fs RMS phase jitter to ensure sufficient margin and de-risk product development. Related ResourcesĪnritsu Adds Tools to VNA Families that Improve Signal Integrity Testing Capability Silicon Labs is the first timing supplier to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device. These designs typically use a mix of other frequencies for CPU and system clocks. ![]() To meet the stringent requirements of 56G SerDes reference clocks, hardware developers often require clocks with sub-100 fs (typical) RMS phase jitter specifications. ![]() Leading manufacturers of switch SoCs, PHYs, FPGAs and ASICs, including Broadcom, Inphi, Intel, MACOM, Marvell, MediaTek and Xilinx, are migrating to 56G PAM4 SerDes technology to support higher bandwidth 100G+ Ethernet and optical networking designs. With this portfolio expansion, Silicon Labs offers a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin. Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM4 SerDes and emerging 112G serial applications. ![]()
0 Comments
Leave a Reply. |
Details
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |